Invention Grant
- Patent Title: Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
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Application No.: US16148325Application Date: 2018-10-01
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Publication No.: US10692842B2Publication Date: 2020-06-23
- Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/07 ; H01L23/00 ; H01L23/498 ; H01L25/10 ; H05K1/18 ; H01L23/31 ; G11C5/06 ; H01L25/075 ; G06F1/18 ; H01L23/367 ; H01L23/538 ; H01L23/50 ; H05K1/02 ; H01L23/36 ; H01L23/48 ; H01L23/525 ; H01L21/56

Abstract:
A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.
Public/Granted literature
Information query
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