A clock generation apparatus includes a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal, a delay line circuit, a switch and a controller. The delay line circuit selects, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, where the selection is based on the selection signal; and thereby generates the delay clock signal. The switch switches a first voltage or a second voltage to the delay line circuit for its operation, where the first voltage further provides power to the pulse generator. The second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal. The controller generates a switch control signal based on a frequency of the delay clock signal.