Invention Grant
- Patent Title: Porous silicon dicing
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Application No.: US15658296Application Date: 2017-07-24
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Publication No.: US10700012B2Publication Date: 2020-06-30
- Inventor: Stephen Alan Fanelli , Richard Hammond
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Seyfarth Shaw LLP
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/683 ; H01L21/304 ; H01L21/306 ; H01L21/78 ; H01L21/02

Abstract:
A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.
Public/Granted literature
- US20180301419A1 POROUS SILICON DICING Public/Granted day:2018-10-18
Information query
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