公开(公告)号：US10748934B2

公开(公告)日：2020-08-18

申请号：US16115352

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Qingqing Liang ,  Stephen Alan Fanelli ,  Sinan Goktepeli

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/51

Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.

公开(公告)号：US10559520B2

公开(公告)日：2020-02-11

申请号：US15975434

申请日：2018-05-09

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Stephen Alan Fanelli

IPC: H01L23/48 ,  H01L21/762 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L25/065 ,  H01L25/11 ,  H01L49/02

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.

公开(公告)号：US11355617B2

公开(公告)日：2022-06-07

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US11277677B1

公开(公告)日：2022-03-15

申请号：US17117940

申请日：2020-12-10

Applicant: QUALCOMM Incorporated

Inventor： George Pete Imthurn ,  Ravi Pramod Kumar Vedula ,  Stephen Alan Fanelli

IPC: H04Q11/00

Abstract: An optically powered switch. An example optically powered switch generally includes a light source configured to output an optical signal. The example optically powered switch generally includes a photodiode configured to convert the optical signal to an electrical signal. The example optically powered switch generally includes a bias and control circuit configured to power at least one radio frequency (RF) switch using the electrical signal.

公开(公告)号：US10700012B2

公开(公告)日：2020-06-30

申请号：US15658296

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L23/544 ,  H01L21/683 ,  H01L21/304 ,  H01L21/306 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

公开(公告)号：US20180233600A1

公开(公告)日：2018-08-16

申请号：US15879109

申请日：2018-01-24

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar Vedula ,  Stephen Alan Fanelli ,  Farid Azzazy

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a channel structure that includes a first oxide layer, a second oxide layer, and a channel region between the first oxide layer and the second oxide layer. The semiconductor device includes a first gate structure proximate to at least three sides of the channel structure. The semiconductor device includes a second gate structure proximate to at least a fourth side of the channel structure.

公开(公告)号：US09837302B1

公开(公告)日：2017-12-05

申请号：US15249112

申请日：2016-08-26

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stephen Alan Fanelli

IPC: H01L49/02 ,  H01L23/66 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H04W88/00

CPC classification number: H01L21/76256 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0694 ,  H01L27/1203 ,  H04W88/005

Abstract: A method includes performing an etching process from a second side of a buried dielectric layer to expose an etch stop layer, where the second side of the buried dielectric layer is opposite a first side of the buried dielectric layer, and where a first semiconductor device is positioned on the first side of the buried dielectric layer. The method further includes forming a second semiconductor device on the second side of the buried dielectric layer.

公开(公告)号：US11309352B2

公开(公告)日：2022-04-19

申请号：US16116744

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stephen Alan Fanelli ,  Yun Han Chu

IPC: H01L27/00 ,  H01L27/20 ,  H03H9/05 ,  H03H9/56 ,  H03H3/02 ,  H03H3/08 ,  H03H9/64 ,  H03H3/007 ,  H03H9/10 ,  H03H9/54 ,  H03H9/46 ,  B81C1/00 ,  H03H1/00

Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.

公开(公告)号：US10784348B2

公开(公告)日：2020-09-22

申请号：US15669704

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/10 ,  H01L23/31 ,  H01L21/02 ,  H01L21/78 ,  H01L27/12 ,  H01L21/20 ,  H01L21/306 ,  H01L21/683 ,  H01L21/762 ,  H01L21/84 ,  H01L23/528 ,  H01L23/00 ,  H01L29/78

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

公开(公告)号：US10680086B2

公开(公告)日：2020-06-09

申请号：US16011430

申请日：2018-06-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  George Pete Imthurn ,  Stephen Alan Fanelli

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.