公开(公告)号：US10290579B2

公开(公告)日：2019-05-14

申请号：US15807169

申请日：2017-11-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Plamen Vassilev Kolev ,  Michael Andrew Stuber ,  Richard Hammond ,  Shiqun Gu ,  Steve Fanelli

IPC: H01L21/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/66 ,  H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H04B1/16 ,  H01L29/66 ,  H01L29/94

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US20180069079A1

公开(公告)日：2018-03-08

申请号：US15255744

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Steve Fanelli ,  Richard Hammond

IPC: H01L29/10 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/66

CPC classification number: H01L23/66 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/408

Abstract: In a particular aspect, a device includes a substrate including a first trap rich layer region and a second trap rich layer region. The first trap rich layer region is separated from the second trap rich layer region by a portion of the substrate. The device further includes a semiconductor device layer including one or more components.

公开(公告)号：US10158030B2

公开(公告)日：2018-12-18

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Gengming Tao ,  Richard Hammond ,  Ranadeep Dutta ,  Matthew Michael Nowak ,  Francesco Carobolante

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US11355617B2

公开(公告)日：2022-06-07

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US10700012B2

公开(公告)日：2020-06-30

申请号：US15658296

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L23/544 ,  H01L21/683 ,  H01L21/304 ,  H01L21/306 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

公开(公告)号：US09847293B1

公开(公告)日：2017-12-19

申请号：US15240952

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Plamen Vassilev Kolev ,  Michael Andrew Stuber ,  Richard Hammond ,  Shiqun Gu ,  Steve Fanelli

IPC: H01L21/48 ,  H01L23/528 ,  H01L27/12 ,  H01L29/06 ,  H01L23/522 ,  H01L23/66 ,  H01L23/532 ,  H01L49/02 ,  H04B1/16

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/53209 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/94 ,  H01L2223/6677 ,  H04B1/16

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US10784348B2

公开(公告)日：2020-09-22

申请号：US15669704

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/10 ,  H01L23/31 ,  H01L21/02 ,  H01L21/78 ,  H01L27/12 ,  H01L21/20 ,  H01L21/306 ,  H01L21/683 ,  H01L21/762 ,  H01L21/84 ,  H01L23/528 ,  H01L23/00 ,  H01L29/78

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

公开(公告)号：US10134837B1

公开(公告)日：2018-11-20

申请号：US15638874

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan Fanelli ,  Richard Hammond

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/3063 ,  H01L21/762

Abstract: A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.

公开(公告)号：US09780210B1

公开(公告)日：2017-10-03

申请号：US15234889

申请日：2016-08-11

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Richard Hammond

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/74 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528 ,  H01L23/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/285 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H04B1/40

CPC classification number: H01L29/7838 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/528 ,  H01L23/66 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654 ,  H01L2223/6677 ,  H01L2224/11 ,  H04B1/006 ,  H04B1/40

Abstract: An integrated circuit structure may include a transistor on a front-side semiconductor layer supported by an isolation layer. The transistor is a first source/drain/body region. The integrated circuit structure may also include a raised source/drain/body region coupled to a backside of the first source/drain/body region of the transistor. The transistor is a raised source/drain/body region extending from the backside of the first source/drain/body region toward a backside dielectric layer supporting the isolation layer. The integrated circuit structure may further include a backside metallization coupled to the raised source/drain/body region.