Invention Grant
- Patent Title: Method of forming layout of semiconductor device
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Application No.: US16178521Application Date: 2018-11-01
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Publication No.: US10707213B2Publication Date: 2020-07-07
- Inventor: Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quangzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quangzhou, Fujian Province
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@646fd940
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L27/108 ; H01L21/027 ; H01L21/033

Abstract:
A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
Public/Granted literature
- US20200111791A1 METHOD OF FORMING LAYOUT OF SEMICONDUCTOR DEVICE Public/Granted day:2020-04-09
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