Invention Grant
- Patent Title: High-voltage transistor with self-aligned isolation
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Application No.: US15754151Application Date: 2015-09-25
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Publication No.: US10707346B2Publication Date: 2020-07-07
- Inventor: Walid M. Hafez , Chia-Hong Jan
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/052204 WO 20150925
- International Announcement: WO2017/052585 WO 20170330
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L29/08

Abstract:
A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.
Public/Granted literature
- US20180248039A1 HIGH-VOLTAGE TRANSISTOR WITH SELF-ALIGNED ISOLATION Public/Granted day:2018-08-30
Information query
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