- 专利标题: Ring voltage-controlled oscillator and phase-locked loop
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申请号: US16312345申请日: 2017-06-21
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公开(公告)号: US10707844B2公开(公告)日: 2020-07-07
- 发明人: Xueyan Wang , Qiang Chen
- 申请人: CSMC TECHNOLOGIES FAB2 CO., LTD.
- 申请人地址: CN Wuxi New District
- 专利权人: CSMC TECHNOLOGIES FAB2 CO., LTD.
- 当前专利权人: CSMC TECHNOLOGIES FAB2 CO., LTD.
- 当前专利权人地址: CN Wuxi New District
- 代理机构: Polsinelli PC
- 优先权: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@5a5307b
- 国际申请: PCT/CN2017/089298 WO 20170621
- 国际公布: WO2018/001146 WO 20180104
- 主分类号: H03K3/03
- IPC分类号: H03K3/03 ; H03K5/134 ; H03B5/20 ; H03L7/099
摘要:
A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.
公开/授权文献
- US20190238122A1 RING VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP 公开/授权日:2019-08-01
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