公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US20240339522A1

公开(公告)日：2024-10-10

申请号：US18292067

申请日：2022-12-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chaoqi XU ,  Shuxian CHEN ,  Chunxia MA ,  Yi ZHANG ,  Penglong XU ,  Feng LIN ,  Ruibin CAO

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/402 ,  H01L29/7816

Abstract: In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.

公开(公告)号：US20240282621A1

公开(公告)日：2024-08-22

申请号：US18571601

申请日：2022-06-17

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wenwen ZHANG ,  Renrui HUANG ,  Yongzhi FANG

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/7681 ,  H01L21/31116 ,  H01L21/76877 ,  H01L23/5226

Abstract: A manufacturing method for a semiconductor device includes: forming an etching termination layer, a first dielectric layer, an auxiliary dielectric layer and a second dielectric layer which are successively stacked from bottom to top; by taking a photoresist layer as an etching barrier layer, patterning the second dielectric layer to obtain a first opening pattern, the bottom of the first opening being provided with a second opening pattern exposing part of the auxiliary dielectric layer; forming a first trench passing through the second dielectric layer and the auxiliary dielectric layer and extending to the first dielectric layer, and forming a second trench passing through the first dielectric layer from the bottom of the first trench and extending to the etching termination layer; and forming a conductive layer in the first and second trenches.

公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US11984813B2

公开(公告)日：2024-05-14

申请号：US17435789

申请日：2020-05-15

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Siyu Zhao ,  Congming Qi ,  Sen Zhang ,  Xiaoyu Shi ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

CPC classification number: H02M3/33592 ,  H02M1/0058 ,  H02M1/38

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

公开(公告)号：US20240079404A1

公开(公告)日：2024-03-07

申请号：US18262100

申请日：2022-01-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun SUN

IPC: H01L27/02

CPC classification number: H01L27/0259

Abstract: The present application relates to an electrostatic protection structure and a preparation method therefor. The electrostatic protection structure comprises a substrate, a buried layer, a first deep well, a second deep well and a third deep well. A well region of the opposite conductivity type and a heavily doped region of the same conductivity type are provided in the first deep well, and well regions and heavily doped regions of the same conductivity type are respectively provided in the second deep well and the third deep well. The first deep well, a first well region and a second well region are floating; a first heavily doped region leads out electrostatic voltage; and a sixth heavily doped region is grounded.

公开(公告)号：US20230268111A1

公开(公告)日：2023-08-24

申请号：US18308399

申请日：2023-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Congying DONG

IPC: H01F17/00 ,  H01L23/522

CPC classification number: H01F17/0013 ,  H01L23/5227 ,  H01F2017/0086

Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.

公开(公告)号：US11532726B2

公开(公告)日：2022-12-20

申请号：US17121360

申请日：2020-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A VDMOS device and a manufacturing method therefor. The method comprises: forming a groove in a semiconductor substrate, wherein the groove comprises a first groove area, a second groove area and a third groove area communicating with the first groove area and the second groove area, and the width of the first groove area is greater than the widths of the second groove area and the third groove area; forming an insulation layer on the semiconductor substrate; forming a first polycrystalline silicon layer on the insulation layer; removing some of the first polycrystalline silicon layer; the first polycrystalline silicon layer forming in the first groove being used as a first electrode of a deep gate; removing all the insulation layer located on the surface of the semiconductor substrate and some of the insulation layer located in the groove; forming a gate oxide layer on the semiconductor substrate; forming a second polycrystalline silicon layer on the gate oxide layer; removing some of the second polycrystalline silicon layer; and the second polycrystalline silicon layer forming in the groove being used as a second electrode of a shallow gate.

公开(公告)号：US20220367722A1

公开(公告)日：2022-11-17

申请号：US17767333

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wangran WU ,  Guangan YANG ,  Feng LIN ,  Guipeng SUN ,  Yaohui WANG ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

公开(公告)号：US20220367682A1

公开(公告)日：2022-11-17

申请号：US17765295

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L21/762

Abstract: A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.