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1.发明公开公开(公告)号：US20240322061A1
公开(公告)日：2024-09-26
申请号：US18578226
申请日：2022-12-13
发明人： Zheng BIAN , Kui XIAO , Aifeng ZHAO , Jinjie HU , Tao YANG
IPC分类号： H01L31/107 , H01L27/144 , H01L31/0216 , H01L31/18
CPC分类号： H01L31/107 , H01L27/1443 , H01L28/20 , H01L31/02164 , H01L31/1804
摘要： The present disclosure relates to a single-photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof. The method includes: obtaining a wafer; patterning and etching a front surface of the base to form a quenching resistor trench and an isolation trench, wherein a width of the isolation trench is greater than a width of the quenching resistor trench; forming an insulation layer on an inner surface of the quenching resistor trench; depositing polycrystalline silicon on the front surface of the base, where the polycrystalline silicon is filled into the quenching resistor trench and seals the quenching resistor trench while the polycrystalline silicon is filled into the isolation trench and does not seal the isolation trench; performing oxidation treatment on the polycrystalline silicon in the isolation trench; filling a light-shielding conductive material into the isolation trench.
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公开(公告)号：US20240304717A1
公开(公告)日：2024-09-12
申请号：US18284052
申请日：2021-08-10
CPC分类号： H01L29/7813 , H01L29/66484 , H01L29/66734 , H01L29/7831
摘要： A semiconductor device having a split gate structure and a method for manufacturing the same. The method includes: obtaining a base formed with a trench; forming a trench wall oxide isolation dielectric on the inner surface of the trench, and forming a split gate by filling the trench with a split gate material; forming a first oxide isolation dielectric on the split gate; forming a silicon nitride isolation dielectric on the first oxide isolation dielectric; filling a second oxide isolation dielectric above the split gate in the trench in the position where the silicon nitride isolation dielectric is not formed; and forming a control gate on the second oxidation isolation dielectric. The isolation structure between the split gate and the control gate is a multi-dielectric structure which has a higher gate-source voltage resistance compared to the those using a single layer of oxide dielectric.
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公开(公告)号：US20240055516A1
公开(公告)日：2024-02-15
申请号：US18260140
申请日：2021-08-17
发明人： Qiong WANG
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7823 , H01L29/0692 , H01L29/0653 , H01L29/402 , H01L29/4238
摘要： This application provides a semiconductor device. The semiconductor device includes: a substrate (101) having a first conductivity type; an STI structure (108) disposed in the substrate (101) in the form of a first ring-like structure and surrounding a portion of the substrate (101), wherein a portion of the substrate surrounded by the STI structure serves as an active area (105); a drain doped region (103) disposed an a top of a central portion of the active area (105) and having a second conductivity type; source doped regions (102) having the second conductivity type, wherein the source doped regions are disposed at the top of the active area (105) on opposite sides of the drain doped region (103) and are spaced apart from the drain doped region (103); a field oxide layer (104) that is disposed over the top surface of the substrate (101) within the active area (105) in the form of a second ring-like structure and surrounds the drain doped region (103); gate polysilicon (106) that is disposed over the top surface of the substrate (101) and is in the form of a third ring-like structure surrounding the field oxide layer (104); and a drift region (107) having the second conductivity type wherein the drift region is disposed in the substrate (101) and surrounds the drain doped region (103).
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公开(公告)号：US11711088B2
公开(公告)日：2023-07-25
申请号：US17419548
申请日：2019-12-23
CPC分类号： H03M1/002 , H03M1/0624
摘要： An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.
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公开(公告)号：US20230163177A1
公开(公告)日：2023-05-25
申请号：US17766406
申请日：2020-08-18
发明人： Huajun JIN , Guipeng SUN
CPC分类号： H01L29/404 , H01L29/401 , H01L29/7816 , H01L29/66681
摘要： The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.
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公开(公告)号：US20230122120A1
公开(公告)日：2023-04-20
申请号：US17265549
申请日：2019-08-15
发明人： Shikang Cheng , Yan Gu , Sen Zhang
IPC分类号： H01L27/02 , H01L29/866 , H01L29/66 , H01L29/06
摘要： A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
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公开(公告)号：US11588049B2
公开(公告)日：2023-02-21
申请号：US17262882
申请日：2019-07-26
发明人： Huajun Jin
摘要： A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).
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公开(公告)号：US20220376094A1
公开(公告)日：2022-11-24
申请号：US17762212
申请日：2020-08-26
发明人： Long ZHANG , Jie MA , Yan GU , Sen ZHANG , Jing ZHU , Jinli GONG , Weifeng SUN , Longxing SHI
IPC分类号： H01L29/739 , H01L29/08 , H01L29/10 , H01L29/06
摘要： An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
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公开(公告)号：US11502194B2
公开(公告)日：2022-11-15
申请号：US17263207
申请日：2019-07-25
发明人： Tse-huang Lo
IPC分类号： H01L21/336 , H01L29/78 , H01L29/423 , H01L29/49 , H01L29/786
摘要： An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.
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公开(公告)号：US11430780B2
公开(公告)日：2022-08-30
申请号：US17266134
申请日：2019-11-01
发明人： Shikang Cheng , Yan Gu , Sen Zhang
IPC分类号： H01L27/02 , H01L21/266 , H01L29/06 , H01L29/74 , H01L29/866
摘要： A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).
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