- 专利标题: Asynchronous clock-less digital logic path planning apparatus and method
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申请号: US15820358申请日: 2017-11-21
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公开(公告)号: US10719079B2公开(公告)日: 2020-07-21
- 发明人: T. Eric Chornenky
- 申请人: NOKOMIS, INC.
- 申请人地址: US PA Charleroi
- 专利权人: NOKOMIS, INC.
- 当前专利权人: NOKOMIS, INC.
- 当前专利权人地址: US PA Charleroi
- 代理机构: AP Patents
- 主分类号: G06F3/06
- IPC分类号: G06F3/06 ; G06F15/00 ; G11C7/22 ; G11C7/10 ; G06F7/76 ; G11C5/02 ; H03K19/177 ; G05D1/00 ; G05D1/02 ; B60R16/023 ; H03K3/037
摘要:
A hybrid of initial time consuming phase of a Single Directional Dijkstra's Algorithm is embodied on an unclocked CMOS logic chip using a parallelized approach with Asynchronous Digital Logic (ADL). The chip includes a a plurality of addressable configurable cells arranged as a multidimensional orthogonal array. The cell array only executes mathematical operations based on a communication between immediately adjacent cells.