Invention Grant
- Patent Title: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
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Application No.: US15701926Application Date: 2017-09-12
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Publication No.: US10725782B2Publication Date: 2020-07-28
- Inventor: Anil Krishna , Yongseok Yi , Eric Rotenberg , Vignyan Reddy Kothinti Naresh , Gregory Michael Wright
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F9/38 ; G06N3/063 ; G06N5/02 ; G06F12/123 ; G06N20/00

Abstract:
Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry. In this manner, the interpretation and updating of usefulness indicators by the memory controller can be varied using the global polarity indicator.
Public/Granted literature
- US20190079772A1 PROVIDING VARIABLE INTERPRETATION OF USEFULNESS INDICATORS FOR MEMORY TABLES IN PROCESSOR-BASED SYSTEMS Public/Granted day:2019-03-14
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