公开(公告)号：US20190065196A1

公开(公告)日：2019-02-28

申请号：US15685519

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Yongseok Yi ,  Vignyan Reddy Kothinti Naresh

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30149 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3848 ,  G06F9/3861

Abstract: Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction system includes a prediction circuit employing reduced operation folding of the history register for indexing a prediction table containing prediction values used to process a consumer instruction when value has not yet been resolved. To avoid the requirement to perform successive logic folding operations to produce a folded context history of a resultant reduced bit width, reduced logic level folding operation of the resultant reduced bit width is employed. Reduced logic level folding operation of the resultant reduced bit width involves using current folded context history from previous contents of a history register as basis for determining a new folded context history. In this manner, logic folding of the history register is faster and operates with reduced power consumption as a result of fewer logic operations.

公开(公告)号：US10725782B2

公开(公告)日：2020-07-28

申请号：US15701926

申请日：2017-09-12

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Yongseok Yi ,  Eric Rotenberg ,  Vignyan Reddy Kothinti Naresh ,  Gregory Michael Wright

IPC: G06F12/00 ,  G06F9/38 ,  G06N3/063 ,  G06N5/02 ,  G06F12/123 ,  G06N20/00

Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry. In this manner, the interpretation and updating of usefulness indicators by the memory controller can be varied using the global polarity indicator.

公开(公告)号：US10437592B2

公开(公告)日：2019-10-08

申请号：US15685519

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Yongseok Yi ,  Vignyan Reddy Kothinti Naresh

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction system includes a prediction circuit employing reduced operation folding of the history register for indexing a prediction table containing prediction values used to process a consumer instruction when value has not yet been resolved. To avoid the requirement to perform successive logic folding operations to produce a folded context history of a resultant reduced bit width, reduced logic level folding operation of the resultant reduced bit width is employed. Reduced logic level folding operation of the resultant reduced bit width involves using current folded context history from previous contents of a history register as basis for determining a new folded context history. In this manner, logic folding of the history register is faster and operates with reduced power consumption as a result of fewer logic operations.

公开(公告)号：US20190079772A1

公开(公告)日：2019-03-14

申请号：US15701926

申请日：2017-09-12

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Yongseok Yi ,  Eric Rotenberg ,  Vignyan Reddy Kothinti Naresh ,  Gregory Michael Wright

IPC: G06F9/38 ,  G06N3/063 ,  G06N5/02

Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry. In this manner, the interpretation and updating of usefulness indicators by the memory controller can be varied using the global polarity indicator.

公开(公告)号：US20190065060A1

公开(公告)日：2019-02-28

申请号：US15688191

申请日：2017-08-28

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Gregory Michael Wright ,  Yongseok Yi ,  Matthew Gilbert ,  Vignyan Reddy Kothinti Naresh

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

Abstract: Caching instruction block header data in block architecture processor-based systems is disclosed. In one aspect, a computer processor device, based on a block architecture, provides an instruction block header cache dedicated to caching instruction block header data. Upon a subsequent fetch of an instruction block, cached instruction block header data may be retrieved from the instruction block header cache (if present) and used to optimize processing of the instruction block. In some aspects, the instruction block header data may include a microarchitectural block header (MBH) generated upon the first decoding of the instruction block by an MBH generation circuit. The MBH may contain static or dynamic information about the instructions within the instruction block. As non-limiting examples, the information may include data relating to register reads and writes, load and store operations, branch information, predicate information, special instructions, and/or serial execution preferences.