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    Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems
    1.
    发明授权
    Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems 有权

    公开(公告)号：US10331447B2

    公开(公告)日：2019-06-25

    申请号：US15690812

    申请日：2017-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Vignyan Reddy Kothinti Naresh ,  Anil Krishna

    IPC: G06F9/38 ,  G06F12/02 ,  G06F9/42 ,  G06F9/30 ,  G06F12/0875

    Abstract: Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems is disclosed. In one aspect, a processor-based system provides a branch prediction circuit including a CRAS. Each CRAS entry within the CRAS includes an address field and a counter field. When a call instruction is encountered, a return address of the call instruction is compared to the address field of a top CRAS entry indicated by a CRAS top-of-stack (TOS) index. If the return address matches the top CRAS entry, the counter field of the top CRAS entry is incremented instead of adding a new CRAS entry for the return address. When a return instruction is subsequently encountered in the instruction stream, the counter field of the top CRAS entry is decremented if its value is greater than zero (0), or, if not, the top CRAS entry is removed from the CRAS.

    BRANCH TARGET PREDICTOR
    2.
    发明申请
    BRANCH TARGET PREDICTOR 审中-公开

    公开(公告)号：US20170371669A1

    公开(公告)日：2017-12-28

    申请号：US15192794

    申请日：2016-06-24

    Applicant: QUALCOMM Incorporated

    Inventor： Anil Krishna ,  Gregory Wright

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3844

    Abstract: A method for predicting a fetch address of a next instruction to be fetched includes selecting, at a processor, a first way identifier or a second way identifier as a way pointer based on an active fetch address and historical prediction data. A first predictor table includes a first entry having the first way identifier and a second predictor table includes a second entry having the second way identifier. The method also includes selecting a first or second fetch address as a predicted fetch address based on the way pointer. A target table includes a first way storing the first fetch address and a second way storing the second fetch address. The first way and the second way are associated with the active fetch address. The first fetch address is associated with the first way identifier and the second fetch address is associated with the second way identifier.

    STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN A REGISTER MAP IN AN OUT-OF-ORDER PROCESSOR
    5.
    发明申请
    STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN A REGISTER MAP IN AN OUT-OF-ORDER PROCESSOR 审中-公开
    在非订单处理者的注册地图中直接存储指令操作的生成值

    公开(公告)号：US20170046154A1

    公开(公告)日：2017-02-16

    申请号：US14860032

    申请日：2015-09-21

    Applicant: QUALCOMM Incorporated

    Inventor： Anil Krishna ,  Rodney Wayne Smith ,  Sandeep Suresh Navada ,  Shivam Priyadarshi ,  Raguram Damodaran

    IPC: G06F9/30

    CPC classification number: G06F9/30112 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    Abstract: Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

    Abstract translation: 提供将指令操作数的窄生成值直接存储在乱序处理器（OoP）的寄存器映射中。 提供了包括指令处理系统的OoP。 指令处理系统包括多个指令处理阶段，其被配置为根据数据流执行流水线处理和执行指令。 指令处理系统还包括寄存器映射表（RMT），其被配置为存储将逻辑寄存器映射到物理寄存器文件（PRF）中的物理寄存器的地址指针，用于存储由消费者指令使用的产生数据，而不覆盖用于稍后执行的逻辑寄存器 订单说明。 在某些方面，指令处理系统被配置为将由执行的指令产生的窄值直接写入（即存储）到RMT中，而不是在写回阶段将窄的产生值写入PRF。

    Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
    7.
    发明授权
    Providing variable interpretation of usefulness indicators for memory tables in processor-based systems 有权

    公开(公告)号：US10725782B2

    公开(公告)日：2020-07-28

    申请号：US15701926

    申请日：2017-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： Anil Krishna ,  Yongseok Yi ,  Eric Rotenberg ,  Vignyan Reddy Kothinti Naresh ,  Gregory Michael Wright

    IPC: G06F12/00 ,  G06F9/38 ,  G06N3/063 ,  G06N5/02 ,  G06F12/123 ,  G06N20/00

    Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry. In this manner, the interpretation and updating of usefulness indicators by the memory controller can be varied using the global polarity indicator.

    Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor
    8.
    发明授权
    Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor 有权

    公开(公告)号：US10108417B2

    公开(公告)日：2018-10-23

    申请号：US14860032

    申请日：2015-09-21

    Applicant: QUALCOMM Incorporated

    Inventor： Anil Krishna ,  Rodney Wayne Smith ,  Sandeep Suresh Navada ,  Shivam Priyadarshi ,  Raguram Damodaran

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

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