Invention Grant
- Patent Title: Memory device for a hierarchical memory architecture
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Application No.: US16025889Application Date: 2018-07-02
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Publication No.: US10725956B2Publication Date: 2020-07-28
- Inventor: Sean Eilert , Mark Leinwander
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F12/08 ; G11C13/00 ; G06F3/06 ; H01L45/00 ; G06F12/02

Abstract:
In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats and may include a Phase Change Memory (PCM) device. An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.
Public/Granted literature
- US20180322085A1 MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE Public/Granted day:2018-11-08
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