Invention Grant
- Patent Title: Negative capacitance FET with improved reliability performance
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Application No.: US16392158Application Date: 2019-04-23
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Publication No.: US10734472B2Publication Date: 2020-08-04
- Inventor: Chun-Chieh Lu , Cheng-Yi Peng , Chien-Hsing Lee , Ling-Yen Yeh , Chih-Sheng Chang , Carlos H. Diaz
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L27/1159 ; H01L21/02 ; H01L29/78 ; H01L21/28 ; H01L27/11585 ; H01L29/51 ; H01L29/66

Abstract:
A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
Public/Granted literature
- US20190252489A1 NEGATIVE CAPACITANCE FET WITH IMPROVED RELIABILITY PERFORMANCE Public/Granted day:2019-08-15
Information query
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