Invention Grant
- Patent Title: Package-on-package assembly with wire bond vias
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Application No.: US15699288Application Date: 2017-09-08
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Publication No.: US10756049B2Publication Date: 2020-08-25
- Inventor: Ellis Chau , Reynaldo Co , Roseann Alatorre , Philip Damberg , Wei-Shun Wang , Se Young Yang
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L21/56 ; H01L25/10 ; H01L25/00 ; H01L23/495 ; H01L21/48 ; H01L23/367 ; H01L23/433 ; H01L25/065 ; H05K3/34

Abstract:
A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
Public/Granted literature
- US20180026007A1 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS Public/Granted day:2018-01-25
Information query
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