A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively. A first pad of the pads, in a plan view, may have a convex edge portion that is convex in a direction away from the first region of the substrate, and a second pad disposed on the first pad, in a plan view, may have a concave edge portion that is concave in a direction toward the first region of the substrate.