- 专利标题: Depletion mode gate in ultrathin FINFET based architecture
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申请号: US16317708申请日: 2016-09-30
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公开(公告)号: US10756210B2公开(公告)日: 2020-08-25
- 发明人: Chia-Hong Jan , Walid M. Hafez , Hsu-Yu Chang , Neville L. Dias , Rahul Ramaswamy , Roman W. Olac-Vaw , Chen-Guan Lee
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2016/055004 WO 20160930
- 国际公布: WO2018/063394 WO 20180405
- 主分类号: H01L51/05
- IPC分类号: H01L51/05 ; H01L29/78 ; H01L29/66 ; H01L29/786
摘要:
A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
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