Invention Grant
- Patent Title: Depletion mode gate in ultrathin FINFET based architecture
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Application No.: US16317708Application Date: 2016-09-30
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Publication No.: US10756210B2Publication Date: 2020-08-25
- Inventor: Chia-Hong Jan , Walid M. Hafez , Hsu-Yu Chang , Neville L. Dias , Rahul Ramaswamy , Roman W. Olac-Vaw , Chen-Guan Lee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/055004 WO 20160930
- International Announcement: WO2018/063394 WO 20180405
- Main IPC: H01L51/05
- IPC: H01L51/05 ; H01L29/78 ; H01L29/66 ; H01L29/786

Abstract:
A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
Public/Granted literature
- US20200066907A1 DEPLETION MODE GATE IN ULTRATHIN FINFET BASED ARCHITECTURE Public/Granted day:2020-02-27
Information query
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