- 专利标题: Methods, systems, and computer program product for implementing an electronic design with optimization maps
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申请号: US16147764申请日: 2018-09-30
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公开(公告)号: US10762260B1公开(公告)日: 2020-09-01
- 发明人: Jian Liu , Jing Wang , Chun-Teh Kao , An-Yu Kuo
- 申请人: Cadence Design Systems, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Vista IP Law Group, LLP
- 主分类号: G06F30/327
- IPC分类号: G06F30/327 ; G06F30/3323 ; G06F111/04
摘要:
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.
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