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7 条记录 (耗时 0.015 秒)

    Methods, systems, and computer program product for implementing an electronic design having embedded circuits
    1.
    发明授权
    Methods, systems, and computer program product for implementing an electronic design having embedded circuits 有权

    公开(公告)号：US10803222B1

    公开(公告)日：2020-10-13

    申请号：US16147762

    申请日：2018-09-30

    申请人： Cadence Design Systems, Inc.

    发明人： Jian Liu ,  Karthikeyan Mahadevan ,  An-Yu Kuo

    IPC分类号： G06F30/00 ,  G06F30/392 ,  G06F30/394

    摘要： Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.

    Methods, systems, and computer program product for implementing an electronic design with optimization maps
    3.
    发明授权
    Methods, systems, and computer program product for implementing an electronic design with optimization maps 有权

    公开(公告)号：US10762260B1

    公开(公告)日：2020-09-01

    申请号：US16147764

    申请日：2018-09-30

    申请人： Cadence Design Systems, Inc.

    发明人： Jian Liu ,  Jing Wang ,  Chun-Teh Kao ,  An-Yu Kuo

    IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F111/04

    摘要： Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

    Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs
    4.
    发明授权
    Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs 有权

    公开(公告)号：US09773086B1

    公开(公告)日：2017-09-26

    申请号：US14791132

    申请日：2015-07-02

    申请人： Cadence Design Systems, Inc.

    发明人： Jian Liu ,  Yanrui Wu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Disclosed are techniques for implementing coplanar waveguide transmission lines in an electronic design. These techniques identify one or more electrically conductive shapes and a plurality of edge segments thereof in an electronic design. A plurality of model trace segments may be constructed based in part or in whole upon a plurality of edge segments. One or more coupled line groups may be generated with the plurality of model trace segments and one or more actual trace segments for a model of the electronic design. Electrical analyses or simulations may be performed on the model to generate electrical analysis results. The electronic design may then be devised or revised based on extracted parameter values of the electrical analysis results.

    System and method for modeling electronic circuit designs
    5.
    发明授权
    System and method for modeling electronic circuit designs 有权

    公开(公告)号：US09864827B1

    公开(公告)日：2018-01-09

    申请号：US14973064

    申请日：2015-12-17

    申请人： Cadence Design Systems, Inc.

    发明人： Jilin Tan ,  Jian Chen ,  Jian Liu ,  An-Yu Kuo ,  Tiejun Yu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports at each interface between one or more sub-zones. Embodiments may further include receiving a selection for an electromagnetic (EM) solver for each of the one or more sub-zones. Embodiments may also include modeling each of the one or more sub-zones.