Invention Grant
- Patent Title: Electrical fuse formation during a multiple patterning process
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Application No.: US15959727Application Date: 2018-04-23
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Publication No.: US10784195B2Publication Date: 2020-09-22
- Inventor: Jiehui Shu , Xiaoqiang Zhang , Haizhou Yin , Moosung M. Chae , Jinping Liu , Hui Zang
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/525

Abstract:
Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
Public/Granted literature
- US20190326209A1 ELECTRICAL FUSE FORMATION DURING A MULTIPLE PATTERNING PROCESS Public/Granted day:2019-10-24
Information query
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