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    Anti-fuse with self aligned via patterning
    1.
    发明授权
    Anti-fuse with self aligned via patterning 有权

    公开(公告)号：US10714422B2

    公开(公告)日：2020-07-14

    申请号：US16161590

    申请日：2018-10-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xiaoqiang Zhang ,  Guoxiang Ning ,  Jiehui Shu

    IPC: H01L23/525 ,  H01L21/768

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.

    Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
    2.
    发明授权
    Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails 有权

    公开(公告)号：US10163914B2

    公开(公告)日：2018-12-25

    申请号：US15603827

    申请日：2017-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

    IPC: H01L29/66 ,  H01L27/11

    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

    E-FUSE STRUCTURE FOR AN INTEGRATED CIRCUIT PRODUCT
    4.
    发明申请
    E-FUSE STRUCTURE FOR AN INTEGRATED CIRCUIT PRODUCT 审中-公开
    集成电路产品的电子熔断器结构

    公开(公告)号：US20150340319A1

    公开(公告)日：2015-11-26

    申请号：US14817546

    申请日：2015-08-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

    IPC: H01L23/525

    CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

    Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

    Narrowed feature formation during a double patterning process
    6.
    发明授权
    Narrowed feature formation during a double patterning process 有权

    公开(公告)号：US10249496B2

    公开(公告)日：2019-04-02

    申请号：US15587597

    申请日：2017-05-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  Xusheng Yu ,  John H. Zhang ,  Xiaoqiang Zhang

    IPC: H01L21/033 ,  H01L23/525 ,  H01L23/532 ,  H01L21/311

    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.

    METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS
    7.
    发明申请
    METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS 审中-公开

    公开(公告)号：US20180261605A1

    公开(公告)日：2018-09-13

    申请号：US15603827

    申请日：2017-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

    IPC: H01L27/11 ,  H01L29/66

    CPC classification number: H01L27/1104 ,  H01L29/66545 ,  H01L29/66818

    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

    DFT structure for TSVs in 3D ICs while maintaining functional purpose
    8.
    发明授权
    DFT structure for TSVs in 3D ICs while maintaining functional purpose 有权
    DFT结构，用于3D IC中的TSV，同时保持功能目的

    公开(公告)号：US09460975B2

    公开(公告)日：2016-10-04

    申请号：US14611496

    申请日：2015-02-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Sukeshwar Kannan ,  Xiaoqiang Zhang ,  Shan Gao

    IPC: H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5256 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC stack, the wafer having thin and thick metal layers; forming first and second TSVs on the wafer, the first and second TSVs laterally separated; forming an eFuse cell between and separated from the first and second TSVs; forming a FF adjacent to the second TSV and on an opposite side of the second TSV from the eFuse cell; connecting the first TSV, the eFuse cell, the second TSV, and the FF in series in an electric circuit; and testing the first and second TSVs prior to bonding the wafer to a subsequent wafer in the 3D IC stack.

    Abstract translation: 提供了在3D IC堆叠中将晶片接合和贴合之后使用eFuse电池测试TSV的方法。 实施例包括提供3D IC堆叠的晶片，该晶片具有薄而厚的金属层; 在晶片上形成第一和第二TSV，第一和第二TSV横向分离; 在第一和第二TSV之间形成eFuse单元并在其间分离; 在第二TSV附近形成与第二TSV相对的FF与eFuse单元; 在电路中串联连接第一TSV，eFuse单元，第二TSV和FF; 以及在将晶片连接到3D IC堆叠中的后续晶片之前测试第一和第二TSV。

    Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure
    10.
    发明授权
    Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure 有权
    形成用于集成电路产品的电熔丝的方法和所得的电熔丝结构

    公开(公告)号：US09159667B2

    公开(公告)日：2015-10-13

    申请号：US13951654

    申请日：2013-07-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

    IPC: H01L21/8238 ,  H01L23/525 ,  H01L21/768 ,  H01L27/06

    CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

    Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

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