公开(公告)号：US10714376B2

公开(公告)日：2020-07-14

申请号：US16016910

申请日：2018-06-25

申请人： GLOBALFOUNDRIES INC.

发明人： Chih-Chiang Chang ,  Haifeng Sheng ,  Jiehui Shu ,  Haigou Huang ,  Pei Liu ,  Jinping Liu ,  Haiting Wang ,  Daniel J. Jaeger

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

摘要： The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10446395B1

公开(公告)日：2019-10-15

申请号：US15950364

申请日：2018-04-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

摘要： Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

公开(公告)号：US10431500B1

公开(公告)日：2019-10-01

申请号：US15936734

申请日：2018-03-27

申请人： GLOBALFOUNDRIES INC.

发明人： Asli Sirman ,  Jiehui Shu ,  Chih-Chiang Chang ,  Huy Cao ,  Haigou Huang ,  Jinping Liu

IPC分类号： H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

摘要： Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

公开(公告)号：US10418272B1

公开(公告)日：2019-09-17

申请号：US15976326

申请日：2018-05-10

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

摘要： At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US10361289B1

公开(公告)日：2019-07-23

申请号：US15933032

申请日：2018-03-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Wei Zhao ,  Shahab Siddiqui ,  Haiting Wang ,  Ting-Hsiang Hung ,  Yiheng Xu ,  Beth Baumert ,  Jinping Liu ,  Scott Beasor ,  Yue Zhong ,  Shesh Mani Pandey

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

摘要： A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

公开(公告)号：US20190131429A1

公开(公告)日：2019-05-02

申请号：US15797837

申请日：2017-10-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/8234

摘要： One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US20180151690A1

公开(公告)日：2018-05-31

申请号：US15875055

申请日：2018-01-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

摘要： Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US20180130656A1

公开(公告)日：2018-05-10

申请号：US15843649

申请日：2017-12-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Judson Robert Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James Mcardle ,  Murat Kerem Akarvardar

IPC分类号： H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

摘要： A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09966272B1

公开(公告)日：2018-05-08

申请号：US15632931

申请日：2017-06-26

申请人： GLOBALFOUNDRIES INC.

发明人： Haifeng Sheng ,  Haigou Huang ,  Tai Fong Chao ,  Jiehui Shu ,  Jinping Liu ,  Xingzhao Shi ,  Laertis Economikos

IPC分类号： H01L21/00 ,  H01L21/3105

CPC分类号： H01L21/31056 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/823878

摘要： The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.