Invention Grant
- Patent Title: Memory device including pass transistors in memory tiers
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Application No.: US16228574Application Date: 2018-12-20
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Publication No.: US10784269B2Publication Date: 2020-09-22
- Inventor: Toru Tanzawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/08
- IPC: G11C16/08 ; H01L27/11526 ; H01L27/11524 ; H01L27/1157 ; H01L27/11556 ; H01L27/11582 ; G11C16/04 ; G11C16/26 ; G11C16/10 ; H01L27/11573 ; H01L27/11575 ; G11C8/12

Abstract:
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.
Public/Granted literature
- US20190123058A1 MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS Public/Granted day:2019-04-25
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