Invention Grant
- Patent Title: Chip scale package structures
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Application No.: US16194802Application Date: 2018-11-19
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Publication No.: US10784297B2Publication Date: 2020-09-22
- Inventor: Yu-Min Lin , Tao-Chih Chang
- Applicant: Industrial Technology Research Institute
- Applicant Address: TW Hsinchu
- Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee Address: TW Hsinchu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4cb362e3
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L23/00 ; H01L23/31

Abstract:
A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.
Public/Granted literature
- US20190206916A1 CHIP SCALE PACKAGE STRUCTURES Public/Granted day:2019-07-04
Information query
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