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    Image sensor package and manufacturing method thereof
    2.
    发明授权
    Image sensor package and manufacturing method thereof 有权

    公开(公告)号：US11569217B2

    公开(公告)日：2023-01-31

    申请号：US17568740

    申请日：2022-01-05

    申请人： Industrial Technology Research Institute

    发明人： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

    IPC分类号： H01L31/0203 ,  H01L25/18 ,  H01L23/00

    摘要： An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

    Chip scale package structures
    3.
    发明授权
    Chip scale package structures 有权

    公开(公告)号：US11538842B2

    公开(公告)日：2022-12-27

    申请号：US17019026

    申请日：2020-09-11

    申请人： Industrial Technology Research Institute

    发明人： Yu-Min Lin ,  Tao-Chih Chang

    IPC分类号： H01L27/146

    摘要： A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

    Package structure and method for connecting components
    4.
    发明授权
    Package structure and method for connecting components 有权

    公开(公告)号：US11355472B2

    公开(公告)日：2022-06-07

    申请号：US16264689

    申请日：2019-02-01

    申请人： Industrial Technology Research Institute

    发明人： Yu-Min Lin ,  Tao-Chih Chang ,  Wei-Chung Lo

    IPC分类号： H01L23/00 ,  H01L27/146

    摘要： A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

    CHIP PACKAGE STRUCTURE
    5.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210035914A1

    公开(公告)日：2021-02-04

    申请号：US16849999

    申请日：2020-04-16

    申请人： Industrial Technology Research Institute

    发明人： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367

    摘要： A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

    HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME
    8.
    发明申请
    HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200075519A1

    公开(公告)日：2020-03-05

    申请号：US16553179

    申请日：2019-08-28

    申请人： Industrial Technology Research Institute

    发明人： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

    IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/31

    摘要： A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.