公开(公告)号：US12009341B2

公开(公告)日：2024-06-11

申请号：US17564197

申请日：2021-12-28

Applicant: Industrial Technology Research Institute

Inventor： Po-Kai Chiu ,  Sheng-Tsai Wu ,  Yu-Min Lin ,  Wen-Hung Liu ,  Ang-Ying Lin ,  Chang-Sheng Chen

IPC: H01L31/0203 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

公开(公告)号：US11569217B2

公开(公告)日：2023-01-31

申请号：US17568740

申请日：2022-01-05

Applicant: Industrial Technology Research Institute

Inventor： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

IPC: H01L31/0203 ,  H01L25/18 ,  H01L23/00

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

公开(公告)号：US11538842B2

公开(公告)日：2022-12-27

申请号：US17019026

申请日：2020-09-11

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang

IPC: H01L27/146

Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a plurality of through silicon via (TSV) and a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

公开(公告)号：US11355472B2

公开(公告)日：2022-06-07

申请号：US16264689

申请日：2019-02-01

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L27/146

Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

公开(公告)号：US20210035914A1

公开(公告)日：2021-02-04

申请号：US16849999

申请日：2020-04-16

Applicant: Industrial Technology Research Institute

Inventor： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367

Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

公开(公告)号：US11587905B2

公开(公告)日：2023-02-21

申请号：US17065527

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20210111153A1

公开(公告)日：2021-04-15

申请号：US17065527

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20200075519A1

公开(公告)日：2020-03-05

申请号：US16553179

申请日：2019-08-28

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

公开(公告)号：US20190252345A1

公开(公告)日：2019-08-15

申请号：US16264689

申请日：2019-02-01

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L27/146

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L27/14636 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16014 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8192 ,  H01L2224/81951 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

公开(公告)号：US20180019178A1

公开(公告)日：2018-01-18

申请号：US15647264

申请日：2017-07-12

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Kuo-Shu Kao ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/31 ,  H01L23/373 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/00 ,  H05K1/02 ,  H01L25/065 ,  H05K1/11 ,  H01L21/56 ,  H01L25/10 ,  H01L23/538 ,  H01L23/492 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24247 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/1023 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/15153 ,  H01L2924/35 ,  H01L2924/37001 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0047 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4688 ,  H05K2201/066 ,  H05K2201/09827 ,  H05K2201/10416

Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.