Invention Grant
- Patent Title: Standard cell architecture for gate tie-off
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Application No.: US16781856Application Date: 2020-02-04
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Publication No.: US10784345B2Publication Date: 2020-09-22
- Inventor: Xiangdong Chen , Venugopal Boynapalli , Hyeokjin Lim
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm Incorporated
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L23/532 ; H01L23/522 ; H01L29/66 ; H01L23/528 ; H01L27/118 ; H01L27/02
Abstract:
A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.
Public/Granted literature
- US20200176563A1 STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF Public/Granted day:2020-06-04
Information query
IPC分类:
