Invention Grant
- Patent Title: Semiconductor device including a shared semiconductor pattern having faceted sidewalls and method for fabricating the same
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Application No.: US15995414Application Date: 2018-06-01
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Publication No.: US10784379B2Publication Date: 2020-09-22
- Inventor: Seok Hoon Kim , Dong Myoung Kim , Dong Suk Shin , Seung Hun Lee , Cho Eun Lee , Hyun Jung Lee , Sung Uk Jang , Edward Nam Kyu Cho , Min-Hee Choi
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee IP Law, P.C.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@75a58664
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/8234 ; H01L21/768 ; H01L21/02 ; H01L29/423 ; H01L29/165 ; H01L27/088 ; H01L29/08 ; H01L29/49 ; H01L27/12
Abstract:
A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
Public/Granted literature
- US20190067484A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2019-02-28
Information query
IPC分类:
