Invention Grant
- Patent Title: Method of forming layout definition of semiconductor device
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Application No.: US16175858Application Date: 2018-10-31
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Publication No.: US10795255B2Publication Date: 2020-10-06
- Inventor: Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@1a398740
- Main IPC: G03F1/36
- IPC: G03F1/36 ; H01L23/538 ; G03F1/38 ; H01L21/033 ; H01L21/308 ; G03F1/00 ; G03F7/20 ; G03F7/00 ; H01L27/108

Abstract:
A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
Public/Granted literature
- US20200105764A1 METHOD OF FORMING LAYOUT DEFINITION OF SEMICONDUCTOR DEVICE Public/Granted day:2020-04-02
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