- Patent Title: Semiconductor structure with partially embedded insulation region
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Application No.: US16105403Application Date: 2018-08-20
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Publication No.: US10796942B2Publication Date: 2020-10-06
- Inventor: Simone Dario Mariani , Fabrizio Fausto Renzo Toia , Marco Sambi , Davide Giuseppe Patti , Marco Morelli , Giuseppe Barillaro
- Applicant: STMICROELECTRONICS S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/762 ; H01L21/02 ; H01L21/306 ; H01L29/06
Abstract:
A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.
Public/Granted literature
- US20200058540A1 Semiconductor Strucure with Partially Embedded Insulation Region Public/Granted day:2020-02-20
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