A semiconductor package comprising: a frame having an opening and including wiring layers and one or more layer of connection vias; a semiconductor chip disposed in the opening and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering the frame and the semiconductor chip and filling the opening; a connection structure disposed on the frame and the active surface of the semiconductor chip, and including one or more redistribution layers electrically connected to the connection pads and the wiring layers; one or more passive components disposed on the connection structure; a molding material covering each of the passive components; and a metal layer covering outer surfaces of each of the frame, the connection structure, and the molding material. The metal layer is connected to a ground pattern included in the wiring layers of the frame.