- 专利标题: Preformed interlayer connections for integrated circuit devices
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申请号: US16316528申请日: 2016-09-26
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公开(公告)号: US10811351B2公开(公告)日: 2020-10-20
- 发明人: Elliot N. Tan
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2016/053830 WO 20160926
- 国际公布: WO2018/057042 WO 20180329
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L21/768 ; H01L23/498
摘要:
A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
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