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公开(公告)号:US12080781B2
公开(公告)日:2024-09-03
申请号:US17129867
申请日:2020-12-21
申请人: Intel Corporation
发明人: Noriyuki Sato , Sarah Atanasov , Abhishek A. Sharma , Bernhard Sell , Chieh-Jen Ku , Elliot N. Tan , Hui Jae Yoo , Travis W. Lajoie , Van H. Le , Pei-Hua Wang , Jason Peck , Tobias Brown-Heft
IPC分类号: H01L29/66 , H01L21/8234 , H01L27/092
CPC分类号: H01L29/66795 , H01L21/823431 , H01L27/0924
摘要: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.
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公开(公告)号:US10409152B2
公开(公告)日:2019-09-10
申请号:US15419147
申请日:2017-01-30
申请人: INTEL CORPORATION
发明人: Charles H. Wallace , Hossam A. Abdallah , Elliot N. Tan , Swaminathan Sivakumar , Oleg Golonzka , Robert M. Bigwood
IPC分类号: G03F1/36 , H01L21/027 , H01L21/308 , G03F1/50 , G03F7/20
摘要: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.
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公开(公告)号:US11854787B2
公开(公告)日:2023-12-26
申请号:US17735006
申请日:2022-05-02
申请人: Intel Corporation
发明人: Richard E. Schenker , Robert L. Bristol , Kevin L. Lin , Florian Gstrein , James M. Blackwell , Marie Krysak , Manish Chandhok , Paul A. Nyhus , Charles H. Wallace , Curtis W. Ward , Swaminathan Sivakumar , Elliot N. Tan
IPC分类号: H01L23/528 , H01L23/522 , H01L23/532 , H01L27/088 , H01L29/78
CPC分类号: H01L23/528 , H01L23/5226 , H01L23/5329 , H01L23/53238 , H01L27/0886 , H01L29/7848
摘要: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
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公开(公告)号:US10811351B2
公开(公告)日:2020-10-20
申请号:US16316528
申请日:2016-09-26
申请人: Intel Corporation
发明人: Elliot N. Tan
IPC分类号: H01L23/522 , H01L21/768 , H01L23/498
摘要: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
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公开(公告)号:US09659860B2
公开(公告)日:2017-05-23
申请号:US14905269
申请日:2013-08-21
申请人: Intel Corporation
发明人: Richard E. Schenker , Elliot N. Tan
IPC分类号: H01L23/532 , H01L21/02 , H01L21/033 , H01L21/311 , H01L23/528 , H01L23/522 , H01L21/768
CPC分类号: H01L23/5226 , H01L21/02115 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.
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公开(公告)号:US11594448B2
公开(公告)日:2023-02-28
申请号:US16435259
申请日:2019-06-07
申请人: Intel Corporation
IPC分类号: H01L21/768 , H01L21/311 , H01L29/423 , H01L29/417
摘要: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.
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公开(公告)号:US20220415897A1
公开(公告)日:2022-12-29
申请号:US17358954
申请日:2021-06-25
申请人: Intel Corporation
发明人: Juan G. Alzate-Vinasco , Travis W. LaJoie , Elliot N. Tan , Kimberly Pierce , Shem Ogadhoh , Abhishek A. Sharma , Bernhard Sell , Pei-Hua Wang , Chieh-Jen Ku
IPC分类号: H01L27/108 , H01L29/786 , H01L29/66
摘要: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.
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8.
公开(公告)号:US10600678B2
公开(公告)日:2020-03-24
申请号:US16246373
申请日:2019-01-11
申请人: Intel Corporation
IPC分类号: H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
摘要: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
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公开(公告)号:US20240241446A1
公开(公告)日:2024-07-18
申请号:US18620262
申请日:2024-03-28
申请人: Intel Corporation
发明人: Marvin Paik , Charles H. Wallace , Leonard Guler , Elliot N. Tan , Shengsi Liu , Vivek Vishwakarma , Izabela Samek , Mohammadreza Soleymaniha
IPC分类号: G03F7/20 , G03F7/00 , H01L21/027
CPC分类号: G03F7/2022 , G03F7/2004 , G03F7/201 , G03F7/70033 , G03F7/7005 , G03F7/70525 , G03F7/7055 , G03F7/70725 , H01L21/0275
摘要: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
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公开(公告)号:US11373950B2
公开(公告)日:2022-06-28
申请号:US17110215
申请日:2020-12-02
申请人: Intel Corporation
发明人: Richard E. Schenker , Robert L. Bristol , Kevin L. Lin , Florian Gstrein , James M. Blackwell , Marie Krysak , Manish Chandhok , Paul A. Nyhus , Charles H. Wallace , Curtis W. Ward , Swaminathan Sivakumar , Elliot N. Tan
IPC分类号: H01L23/528 , H01L23/522 , H01L23/532 , H01L27/088 , H01L29/78
摘要: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
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