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    Pattern decomposition lithography techniques
    3.
    发明授权
    Pattern decomposition lithography techniques 有权

    公开(公告)号：US10409152B2

    公开(公告)日：2019-09-10

    申请号：US15419147

    申请日：2017-01-30

    Applicant: INTEL CORPORATION

    Inventor： Charles H. Wallace ,  Hossam A. Abdallah ,  Elliot N. Tan ,  Swaminathan Sivakumar ,  Oleg Golonzka ,  Robert M. Bigwood

    IPC: G03F1/36 ,  H01L21/027 ,  H01L21/308 ,  G03F1/50 ,  G03F7/20

    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

    Vertical edge blocking (VEB) technique for increasing patterning process margin
    4.
    发明授权
    Vertical edge blocking (VEB) technique for increasing patterning process margin 有权

    公开(公告)号：US11594448B2

    公开(公告)日：2023-02-28

    申请号：US16435259

    申请日：2019-06-07

    Applicant: Intel Corporation

    Inventor： Leonard P. Guler ,  Chul-Hyun Lim ,  Paul A. Nyhus ,  Elliot N. Tan ,  Charles H. Wallace

    IPC: H01L21/768 ,  H01L21/311 ,  H01L29/423 ,  H01L29/417

    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

    MULTILEVEL WORDLINE ASSEMBLY FOR EMBEDDED DRAM
    5.
    发明申请
    MULTILEVEL WORDLINE ASSEMBLY FOR EMBEDDED DRAM 有权

    公开(公告)号：US20220415897A1

    公开(公告)日：2022-12-29

    申请号：US17358954

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Elliot N. Tan ,  Kimberly Pierce ,  Shem Ogadhoh ,  Abhishek A. Sharma ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

    IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

    Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

    Pattern decomposition lithography techniques
    9.
    发明授权
    Pattern decomposition lithography techniques 有权

    公开(公告)号：US11107786B2

    公开(公告)日：2021-08-31

    申请号：US16692589

    申请日：2019-11-22

    Applicant: INTEL CORPORATION

    Inventor： Charles H. Wallace ,  Hossam A. Abdallah ,  Elliot N. Tan ,  Swaminathan Sivakumar ,  Oleg Golonzka ,  Robert M. Bigwood

    IPC: G03F7/20 ,  H01L23/00 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

    Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

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