Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.