- Patent Title: Program verification time reduction in non-volatile memory devices
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Application No.: US16146814Application Date: 2018-09-28
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Publication No.: US10832766B2Publication Date: 2020-11-10
- Inventor: Ali Khakifirooz , Pranav Kalavade , Uday Chandrasekhar , Trupti Bemalkhedkar , Chang Wan Ha
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C11/56 ; G11C16/04 ; G11C16/34

Abstract:
An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.
Public/Granted literature
- US20190043563A1 PROGRAM VERIFICATION TIME REDUCTION IN NON-VOLATILE MEMORY DEVICES Public/Granted day:2019-02-07
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