Invention Grant
- Patent Title: Pattern evaluation device
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Application No.: US16310830Application Date: 2016-07-22
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Publication No.: US10854420B2Publication Date: 2020-12-01
- Inventor: Miki Isawa , Ayumi Doi , Kazuhisa Hasumi
- Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
- Applicant Address: JP Tokyo
- Assignee: HITACHI HIGH-TECH CORPORATION
- Current Assignee: HITACHI HIGH-TECH CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- International Application: PCT/JP2016/071478 WO 20160722
- International Announcement: WO2018/016062 WO 20180125
- Main IPC: H01J37/28
- IPC: H01J37/28 ; H01J37/22 ; G01N23/2251 ; G06T7/00

Abstract:
A pattern evaluation device has measurement or inspection conditions, supplied for the measurement and inspection of a replica produced by transferring a pattern for a semiconductor wafer or the like, which can be easily set, and with which recipes can be easily generated, when measurement and inspection conditions for the semiconductor wafer or the like and recipes in which these conditions are stored have been prepared in advance. The pattern evaluation device in which a pattern formed on the semiconductor wafer is evaluated on the basis of image data or signal waveforms obtained on the basis of beam irradiation or probe scanning of the semiconductor wafer, wherein the device conditions for evaluating the semiconductor wafer are converted to device conditions for evaluating a replica obtained by transferring a part of a pattern of the semiconductor wafer, and the converted device conditions are used to evaluate the replica.
Public/Granted literature
- US20200098543A1 PATTERN EVALUATION DEVICE Public/Granted day:2020-03-26
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