Invention Grant
- Patent Title: Method to reduce etch variation using ion implantation
-
Application No.: US16578360Application Date: 2019-09-22
-
Publication No.: US10854729B2Publication Date: 2020-12-01
- Inventor: Tsan-Chun Wang , Ziwei Fang , Chii-Horng Li , Tze-Liang Lee , Chao-Cheng Chen , Syun-Ming Jang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/10 ; H01L29/165 ; H01L21/8238 ; H01L21/306 ; H01L21/3065 ; H01L21/265

Abstract:
The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
Public/Granted literature
- US20200020784A1 METHOD TO REDUCE ETCH VARIATION USING ION IMPLANTATION Public/Granted day:2020-01-16
Information query
IPC分类: