Invention Grant
- Patent Title: Improving size and efficiency of dies
-
Application No.: US15774091Application Date: 2015-12-23
-
Publication No.: US10886228B2Publication Date: 2021-01-05
- Inventor: Mathew J. Manusharow , Jonathan Rosenfeld
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C
- International Application: PCT/US2015/000300 WO 20151223
- International Announcement: WO2017/111790 WO 20170629
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/538 ; H01L25/065 ; H01L21/48 ; H01L23/498 ; H01L23/64 ; H01L25/00

Abstract:
An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
Public/Granted literature
- US20180331042A1 SIZE AND EFFICIENCY OF DIES Public/Granted day:2018-11-15
Information query
IPC分类: