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    HIGH DENSITY INTERCONNECT DEVICE AND METHOD
    2.
    发明申请
    HIGH DENSITY INTERCONNECT DEVICE AND METHOD 有权

    公开(公告)号：US20220028790A1

    公开(公告)日：2022-01-27

    申请号：US17494404

    申请日：2021-10-05

    Applicant: Intel Corporation

    Inventor： Mihir K. Roy ,  Mathew J. Manusharow

    IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

    Integrated circuit package substrate
    7.
    发明授权
    Integrated circuit package substrate 有权

    公开(公告)号：US10522455B2

    公开(公告)日：2019-12-31

    申请号：US16264195

    申请日：2019-01-31

    Applicant: INTEL CORPORATION

    Inventor： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

    IPC: H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

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