Invention Grant
- Patent Title: Apparatus and methods for reducing clock-ungating induced voltage droop
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Application No.: US16193410Application Date: 2018-11-16
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Publication No.: US10890937B2Publication Date: 2021-01-12
- Inventor: Martin Saint-Laurent , Lam Ho , Carlos Andres Rodriguez Ancer , Bhavin Shah
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F1/03
- IPC: G06F1/03 ; G06F1/08 ; G06F1/3206 ; G06F1/3237 ; G06F1/324 ; G06F1/10 ; H03K3/012 ; H03K19/00 ; H03K5/131 ; H03K21/40

Abstract:
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.
Public/Granted literature
- US20190086946A1 APPARATUS AND METHODS FOR REDUCING CLOCK-UNGATING INDUCED VOLTAGE DROOP Public/Granted day:2019-03-21
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