- Patent Title: Scan optimization from stacking multiple reliability specifications
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Application No.: US16232185Application Date: 2018-12-26
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Publication No.: US10892024B2Publication Date: 2021-01-12
- Inventor: Ankit Vashi , Harish Reddy Singidi , Kishore Kumar Muchherla
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C11/406 ; G11C16/26 ; G11C29/10 ; G06F11/00 ; G11C16/10
Abstract:
A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.
Public/Granted literature
- US20200211664A1 SCAN OPTIMIZATION FROM STACKING MULTIPLE RELIABILITY SPECIFICATIONS Public/Granted day:2020-07-02
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