Invention Grant
- Patent Title: Controller architecture for reducing on-die capacitance
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Application No.: US16746365Application Date: 2020-01-17
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Publication No.: US10896721B2Publication Date: 2021-01-19
- Inventor: Nitin Kumar Chhabra
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Holzer Patel Drennan
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/409 ; G11C11/4076 ; G11C11/408 ; G11C7/10 ; G06F13/42 ; G11C11/4096 ; G11C7/22

Abstract:
The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
Public/Granted literature
- US20200152254A1 CONTROLLER ARCHITECTURE FOR REDUCING ON-DIE CAPACITANCE Public/Granted day:2020-05-14
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