Invention Grant
- Patent Title: Staged power on/off sequence at the I/O phy level in an interchip interface
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Application No.: US15215636Application Date: 2016-07-21
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Publication No.: US10901936B2Publication Date: 2021-01-26
- Inventor: Daniel M. Dreps , Prasanna Jayaraman , Michael B. Spear
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Law Office of Jim Boice
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/22
![Staged power on/off sequence at the I/O phy level in an interchip interface](/abs-image/US/2021/01/26/US10901936B2/abs.jpg.150x150.jpg)
Abstract:
A method, system, and/or computer program product controls transitions from a first bandwidth to a second bandwidth in a bus within a multi-processor computer. A bus controller predicts a bandwidth transition requirement for a bus in a multi-processor computer, and transitions the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement. The bus controller checks an actual transitioning requirement of the bus in the computer, such that the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processor processors in the computer. In response to the actual transitioning requirement matching the predicted bandwidth transition requirement, the bus controller directions a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.
Public/Granted literature
- US20180024963A1 STAGED POWER ON/OFF SEQUENCE AT THE I/O PHY LEVEL IN AN INTERCHIP INTERFACE Public/Granted day:2018-01-25
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