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1.发明授权公开(公告)号：US12111684B2
公开(公告)日：2024-10-08
申请号：US18455101
申请日：2023-08-24
发明人： Douglas J. Malone , Andreas H. A. Arp , Franklin M. Baez , Daniel M. Dreps , Jason Lee Frankel , Chad Andrew Marquart , Ching Lung Tong , Lily Jielu Zhang
摘要： A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
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公开(公告)号：US20220308564A1
公开(公告)日：2022-09-29
申请号：US17209574
申请日：2021-03-23
发明人： Kirk D. Peterson , Steven Paul Ostrander , Stephanie E Allard , Charles L. Reynolds , Sungjun Chun , Daniel M. Dreps , Brian W. Quinlan , Sylvain Pharand , Jon Alfred Casey , David Edward Turnbull , Pascale Gagnon , Jean Labonte , Jean-Francois Bachand , Denis Blanchard
IPC分类号： G05B19/418
摘要： Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.
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公开(公告)号：US20200166977A1
公开(公告)日：2020-05-28
申请号：US16201511
申请日：2018-11-27
摘要： A method, a system and a computer program product for reconfiguring hardware network topology including graphics processor units (GPU) and central processing unit (CPU) interconnectivity on or across compute nodes of a rack-mount server. The re-configurability is based on detected thermal throttling or thermal hot spots when running workloads. For network re-configurability, a user can directly connect high-speed cable links between CPU/GPU connectors and between GPU/GPU connectors on a same PCB compute node, or across two PCB compute nodes as suggested by a control processor to avoid thermal and power hotspots when running the workload. The method recommends and generates a system map of the hardware network topology known to avoid/mitigate thermal throttling, and instructs a configuration of CPUs and GPUs such that GPUs are assigned to workloads at locations for mitigating thermal throttling based on detected thermal hot spots and power hot spots to optimize workload performance.
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公开(公告)号：US10102884B2
公开(公告)日：2018-10-16
申请号：US14920610
申请日：2015-10-22
发明人： Paul W. Coteus , Daniel M. Dreps , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Todd E. Takken
摘要： Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
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公开(公告)号：US20180026620A1
公开(公告)日：2018-01-25
申请号：US15723491
申请日：2017-10-03
发明人： Daniel M. Dreps
IPC分类号： H03K17/04 , H05K3/32 , H03K17/687 , H03K17/082 , H05K3/30 , H02H3/20 , G06F13/40
CPC分类号： H03K17/04 , G06F13/4072 , G06F2213/0042 , H02H3/20 , H03K17/0822 , H03K17/687 , H05K3/303 , H05K3/32 , Y10T29/413
摘要： Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.
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公开(公告)号：US09686053B2
公开(公告)日：2017-06-20
申请号：US14833643
申请日：2015-08-24
IPC分类号： G01R31/28 , H04L1/24 , G06F11/07 , G06F11/30 , G06F11/22 , G06F11/263 , G06F11/273 , H04L12/26
CPC分类号： H04L1/242 , G06F11/076 , G06F11/2221 , G06F11/263 , G06F11/273 , G06F11/3027 , H04L43/0823 , H04L43/50 , H04L2001/0094
摘要： Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
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公开(公告)号：US20160349325A1
公开(公告)日：2016-12-01
申请号：US14833409
申请日：2015-08-24
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/3177 , G06F13/4282
摘要： Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
摘要翻译： 本公开的实施例提供了使用符合性模型来确定信道与总线的芯片I / O电路在其端部的兼容性的方法。 该方法包括识别至少一个设计标准并获得已知达到设计标准的合格信号通道的频域参数的边界集合。 在某些实施例中，边界集可以使用遗传算法导出。 该方法还包括通过将特定信道的频域参数的值与已知的兼容信道的频域参数的一个或多个边界集合进行比较来验证特定信号信道是否顺从。
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公开(公告)号：US20160134362A1
公开(公告)日：2016-05-12
申请号：US14538118
申请日：2014-11-11
IPC分类号： H04B10/038 , H04Q11/00 , H04L12/40 , G02B6/35 , H04L12/707
CPC分类号： H04B10/038 , G06F13/00 , H04B10/075 , H04B10/25 , H04L12/40182 , H04L45/22 , H04Q11/0066 , H04Q2011/0081
摘要： Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.
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公开(公告)号：US09219473B2
公开(公告)日：2015-12-22
申请号：US13840061
申请日：2013-03-15
发明人： Daniel M. Dreps
IPC分类号： H02H3/20 , H03K17/04 , G06F13/40 , H03K17/082
CPC分类号： H03K17/04 , G06F13/4072 , G06F2213/0042 , H02H3/20 , H03K17/0822 , H03K17/687 , H05K3/303 , H05K3/32 , Y10T29/413
摘要： Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.
摘要翻译： 提供通用串行总线（USB）保护电路。 电路包括串联连接在焊盘和接地之间的多个第一晶体管。 电路还包括串联连接在焊盘和电源电压之间的多个第二晶体管。 该电路还包括控制电路，该控制电路向多个第一晶体管中的每一个施加相应的偏置电压，并对多个第二晶体管中的每个施加相应的偏置电压。 偏置电压被配置为：当焊盘的焊盘电压在标称电压范围内时，关闭多个第一晶体管并关闭多个第二晶体管; 当焊盘电压增加到高于标称电压范围时，顺序地接通多个第一晶体管; 并且当焊盘电压降低到额定电压范围以下时，依次打开多个第二晶体管。
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公开(公告)号：US20140149627A1
公开(公告)日：2014-05-29
申请号：US13685583
申请日：2012-11-26
IPC分类号： G06F13/38
CPC分类号： G06F13/423 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.
摘要翻译： 用于在PCI Express接口处检测一个或多个信号的系统包括被配置为在PCI Express接口处接收信号的接收机，以及被配置为基于电平感测来检测一个或多个信号的峰值检测器，并且识别一个或多个数据采样 点设置振幅阈值。 比较器被配置为将接收信号的幅度与幅度阈值进行比较，并且处理器被配置为当信号的幅度是大于或等于幅度的至少一个时，确认接收信号是有效信号 阈值超过预定义的时间段。 处理器还被配置为禁用可以检测一个或多个低频信号的信号检测器。 该系统还包括测试器，其被配置为测试检测到的信号是否正确。
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