Provided is a non-volatile memory device including a control logic, a semiconductor layer, a resistance switching layer, a gate oxide layer, and a gate stack including a plurality of gates and a plurality of insulating layers, wherein the plurality of gates and the plurality of insulating layers are stacked alternately with each other. The resistance switching layer is provided between the semiconductor layer and the gate stack. The gate oxide layer is provided between the resistance switching layer and the gate stack. A cell string including a plurality of memory cells is formed by the gate stack, the resistance switching layer, and the gate oxide layer.