中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

94 records (took 0.028 seconds)

    Memory controller with high data reliability, a memory system having the same, and an operation method of the memory controller
    5.
    发明授权
    Memory controller with high data reliability, a memory system having the same, and an operation method of the memory controller 有权

    公开(公告)号：US11256563B2

    公开(公告)日：2022-02-22

    申请号：US16882601

    申请日：2020-05-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongho Lee ,  Youngjin Cho ,  Seungwon Lee

    IPC: G11C29/44 ,  G06F11/10 ,  H03M13/09 ,  H03M13/25

    Abstract: A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.

    Variable resistance memory device
    6.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US11239416B2

    公开(公告)日：2022-02-01

    申请号：US16691818

    申请日：2019-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Yoon ,  Soichiro Mizusaki ,  Youngjin Cho

    IPC: H01L45/00

    Abstract: A variable resistance memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction, the second direction intersecting the first direction on the first conductive line, a fixed resistance layer between the first conductive line and the second conductive line, and a variable resistance layer between the first conductive line and the second conductive line, wherein the fixed resistance layer and the variable resistance layer are electrically connected in parallel to each other between the first conductive line and the second conductive line.

    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY
    9.
    发明申请
    SYSTEMS AND METHODS FOR WRITE AND FLUSH SUPPORT IN HYBRID MEMORY 审中-公开

    公开(公告)号：US20180329651A1

    公开(公告)日：2018-11-15

    申请号：US15669851

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Heehyun Nam ,  Youngjin Cho ,  Sun-Young Lim

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685

    Abstract: A memory module includes a memory controller including: a host layer; a media layer coupled to a non-volatile memory; and a logic core coupled to the host layer, the media layer, and a volatile memory, the logic core storing a first write group table including a plurality of rows, and the logic core being configured to: receive a persistent write command including a cache line address and a write group identifier; receive data associated with the persistent write command; write the data to the volatile memory at the cache line address; store the cache line address in a selected buffer of a plurality of buffers in a second write group table, the selected buffer corresponding to the write group identifier; and update a row of the first write group table to identify locations of the selected buffer containing valid entries, the row corresponding to the write group identifier.

Patent Agency Ranking