Invention Grant
- Patent Title: Manage source line bias to account for non-uniform resistance of memory cell source lines
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Application No.: US16909821Application Date: 2020-06-23
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Publication No.: US10910069B2Publication Date: 2021-02-02
- Inventor: Murong Lang , Zhenming Zhou , Deepanshu Dutta
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/26 ; G11C16/04 ; G11C16/24 ; H01L27/11524 ; H01L27/11565 ; H01L27/11556 ; H01L27/11582 ; H01L27/11519 ; H01L27/1157

Abstract:
Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
Public/Granted literature
- US20200321060A1 MANAGE SOURCE LINE BIAS TO ACCOUNT FOR NON-UNIFORM RESISTANCE OF MEMORY CELL SOURCE LINES Public/Granted day:2020-10-08
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