-
公开(公告)号：US10541038B2
公开(公告)日：2020-01-21
申请号：US16205165
申请日：2018-11-29
发明人： Yu-Chung Lien , Xiang Yang , Zhenming Zhou , Deepanshu Dutta , Huai-Yuan Tseng
摘要： An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
-
公开(公告)号：US20190392894A1
公开(公告)日：2019-12-26
申请号：US16019141
申请日：2018-06-26
发明人： Dengtao Zhao , Deepanshu Dutta , Zhenming Zhou
IPC分类号： G11C11/56 , G11C16/26 , G11C16/24 , G11C16/34 , H01L27/11556 , G11C16/04 , G11C16/30 , H01L27/11582
摘要： A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.
-
公开(公告)号：US20190378583A1
公开(公告)日：2019-12-12
申请号：US16205165
申请日：2018-11-29
发明人： Yu-Chung Lien , Xiang Yang , Zhenming Zhou , Deepanshu Dutta , Huai-Yuan Tseng
摘要： An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
-
公开(公告)号：US09805809B1
公开(公告)日：2017-10-31
申请号：US15253864
申请日：2016-08-31
发明人： Zhenming Zhou , Guirong Liang , Gerrit Jan Hemink , Dana Lee , Chandu Gorla , Sarath Puthenthermadam , Deepanshu Dutta
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3427
摘要： Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising a plurality of word lines. A controller is configured to perform a read operation on one or more word lines adjacent to a target word line. A controller is configured to determine a read setting for application to a target word line based on a result of a read operation on one or more word lines adjacent to the target word line. A controller is configured to perform a read operation on a target word line using a determined read setting.
-
公开(公告)号：US11101001B2
公开(公告)日：2021-08-24
申请号：US16021290
申请日：2018-06-28
发明人： Henry Chin , Zhenming Zhou
摘要： A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
-
6.发明授权公开(公告)号：US10910069B2
公开(公告)日：2021-02-02
申请号：US16909821
申请日：2020-06-23
发明人： Murong Lang , Zhenming Zhou , Deepanshu Dutta
IPC分类号： G11C16/06 , G11C16/26 , G11C16/04 , G11C16/24 , H01L27/11524 , H01L27/11565 , H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/1157
摘要： Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
-
7.发明申请公开(公告)号：US20200321060A1
公开(公告)日：2020-10-08
申请号：US16909821
申请日：2020-06-23
发明人： Murong Lang , Zhenming Zhou , Deepanshu Dutta
IPC分类号： G11C16/26 , G11C16/04 , G11C16/24 , H01L27/11524 , H01L27/11565 , H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/1157
摘要： Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
-
8.发明申请公开(公告)号：US20200098434A1
公开(公告)日：2020-03-26
申请号：US16142386
申请日：2018-09-26
发明人： Murong Lang , Zhenming Zhou , Deepanshu Dutta
IPC分类号： G11C16/26 , G11C16/04 , G11C16/24 , H01L27/11524 , H01L27/1157 , H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/11565
摘要： Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
-
公开(公告)号：US11087849B2
公开(公告)日：2021-08-10
申请号：US16021282
申请日：2018-06-28
发明人： Henry Chin , Zhenming Zhou
摘要： A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
-
公开(公告)号：US10825513B2
公开(公告)日：2020-11-03
申请号：US16019141
申请日：2018-06-26
发明人： Dengtao Zhao , Deepanshu Dutta , Zhenming Zhou
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26 , G11C16/24 , G11C16/34 , H01L27/11556 , G11C16/30 , H01L27/11582
摘要： A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.014 秒)
